The present invention is generally related to resistive switching devices. More particularly, embodiments according to the present invention provide a method and a structure for forming an interconnect structure for a stacked resistive switching device. The present invention can be applied to non-volatile memory devices but it should be recognized that the present invention can have a much broader range of applicability.
The success of semiconductor devices has been mainly driven by an intensive transistor down-scaling process. However, as field effect transistors (FET) approach sizes less than 100 nm, problems such as the short channel effect degrade device performance. Moreover, such sub 100 nm device sizes can lead to sub-threshold slope non-scaling and increase in power dissipation. It is generally believed that transistor-based memories such as those commonly known as Flash may approach an end to scaling within a decade. Flash memory is one type of non-volatile memory device.
Other non-volatile random access memory (RAM) devices such as ferroelectric RAM (Fe RAM), magneto-resistive RAM (MRAM), organic RAM (ORAM), and phase change RAM (PCRAM), among others, have been explored as next generation memory devices. These devices often require new materials and device structures to couple with silicon-based devices to form a memory cell, which lack one or more key attributes. For example, Fe-RAM and MRAM devices have fast switching characteristics and good programming endurance, but their fabrication is not CMOS compatible and size is usually large. Switching a PCRAM device requires a large amount of power. Organic RAM or ORAM is incompatible with large volume silicon-based fabrication and device reliability is usually poor.
From the above, a new semiconductor device structure and integration is desirable